1 VCC 3.3 V Power Supply[reference:89]
2 GND Ground
3 DA0+ TMDS Data Channel 0 Positive Input
4 DA0- TMDS Data Channel 0 Negative Input
5 GND Ground
6 DA1+ TMDS Data Channel 1 Positive Input
7 DA1- TMDS Data Channel 1 Negative Input
8 GND Ground
9 DA2+ TMDS Data Channel 2 Positive Input
10 DA2- TMDS Data Channel 2 Negative Input
11 GND Ground
12 DCLK+ TMDS Clock Channel Positive Input
13 DCLK- TMDS Clock Channel Negative Input
14 GND Ground
15 SCL I2C Clock (DDC Interface)[reference:90]
16 SDA I2C Data (DDC Interface)[reference:91]
17 VCC 3.3 V Power Supply[reference:92]
18 GND Ground
19 DB0+ TMDS Data Channel 0 Positive Output
20 DB0- TMDS Data Channel 0 Negative Output
21 GND Ground
22 DB1+ TMDS Data Channel 1 Positive Output
23 DB1- TMDS Data Channel 1 Negative Output
24 GND Ground
25 DB2+ TMDS Data Channel 2 Positive Output
26 DB2- TMDS Data Channel 2 Negative Output
27 GND Ground
28 DCLK_OUT+ TMDS Clock Channel Positive Output
29 DCLK_OUT- TMDS Clock Channel Negative Output
30 GND Ground
31 VDD 1.2 V Core Power Supply[reference:93]
32 GND Ground
33 VDD 1.2 V Core Power Supply[reference:94]
34 GND Ground
35 VDD 1.2 V Core Power Supply[reference:95]
36 GND Ground
37 NC No Connect
38 NC No Connect
39 NC No Connect
40 NC No Connect
41 SPDIF_IN Audio Return Channel Input (S/PDIF)[reference:96]
42 ARC_OUT Audio Return Channel Output[reference:97]
43 GND Ground
44 PD Power Down (Active Low)
45 VCC 3.3 V Power Supply[reference:98]
46 VDD 1.2 V Core Power Supply[reference:99]
47 GND Ground
48 VCC 3.3 V Power Supply[reference:100]